The present invention relates to a method and/or architecture for built-in self test (BIST) devices generally and, more particularly, to a method and/or architecture for memory architecture independent configurable BIST devices.
Conventional built-in self test (BIST) designs for memory blocks are customized for each type of memory block. The BIST designs must give due consideration to a memory size and architecture (scrambling of bits) used within the memory blocks. In the process, the BIST design becomes a specific component that cannot be reused across different products. All of the procedures for testing the memory block are fixed in the BIST design and thus and cannot be changed during the life cycle of the memory block. Also the same BIST design cannot be reused if targeted for different memory architectures.
Referring to FIG. 1, a block diagram of a general structure of a conventional BIST design is shown. A state machine 100 is hard coded and has preset states. The state machine 100 presents the preset states as a signal (i.e., CNTR) to a memory block 102, an address generator 104, and a data generator 106. The address generator 104 presents a signal (i.e., ADDR) to the memory block 102 in response to the signal CNTR. The data generator 106 presents a signal (i.e., DIN) to the memory block 102 and another signal (i.e., DATA2) to a comparator 108 in response to the signal CNTR. The comparator 108 compares an output signal (i.e., DOUT) from the memory block 102 with the signal DATA2 to present a signal (i.e., RESULT). In each BIST test, the signals CNTR, ADDR, and DIN are used to write predetermined data to the memory block 102, read data from the memory block 102, or both. If the comparator 108 determines that the signal DOUT matches the signal DATA2, then the memory device 102 passes the BIST test in progress.
FIG. 2 is a flow diagram for a sequence of BIST tests. The sequence executes a first test (i.e., block 110) to produce a first result. Subsequent tests (i.e., blocks 112-114) are then executed to produce additional results. After all of the BIST tests have completed, a signal (i.e., BIST DONE) is presented to signal a completion of the testing. Should any procedure of the individual BIST tests 110-114 require additions, modifications, deletions or rearranging, then the state machine 100 and possibly the address generator 104 and the data generator 106 will require a redesign.
The present invention concerns a circuit that may be used to support testing of a memory block. The circuit generally comprises a decoder and a generator. The decoder may be configured to (i) decode a command signal into an address field, an operation field, and a data field and (ii) present a control signal to the memory block in response to the operation field. The generator may be configured to (i) present an address signal to the memory block in response to the address field and (ii) present a data signal to the memory block in response to the data field.
The objects, features and advantages of the present invention include providing a method and/or architecture for configurable and memory architecture independent built-in self test for memory blocks, devices and circuits that may (i) be reused across different memory architectures and organizations, (ii) execute test procedures of complexity O(n), (iii) reduce test time by executing only selective procedures, (iv) execute some test procedures of a complexity O(n2) using an extended instruction set, and/or (v) change the test procedures over a life cycle of the memory device.